preliminary this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 21446 rev: a amendment/ 0 issue date: april 1997 NET186-EVAL-KT am186 es and pcnet-isa ii based stand-alone evaluation platform distinctive characteristics n am186 es-40 mhz microcontroller 80c186 compatibility glueless interface to psram, sram, flash, and rom memory systems demultiplexed address/data bus two dma channels 32 programmable i/o (pio) pins n am79c961a pcnet-isa ii ethernet controller single-chip ethernet controller for direct interface to isa and eisa buses supports ieee 802.3/ansi 8802-3 ethernet standards supports full duplex operation on the 10base-t, aui and gpsi ports supports magic packet technology for waking up remote ethernet nodes software compatible with am7990/am79c90 lance /clance register and descriptor architecture n communication ports two rs-232 serial ports driven by the am186es via two db-9 dce connectors one 10base-t ethernet port driven by the pcnet-isa ii via an rj-45 connector n expansion bus am186 expansion interface n memory one 512kbytes sram one 512kbytes flash (am29f400) capable of addressing up to 1mbytes of flash software e86mon monitor program with source code utility programs for pcnet-isa ii with source codes pal equations for board setup general description the net186 evaluation board meets the needs of cus- tomers working with embedded networking control applications using the am186es microcontroller and the pcnet-isa ii single-chip ethernet controller. this board provides a complete stand-alone, microcontrol- ler and ethernet-based evaluation in a low-cost, excep- tionally small form-factor product. this evaluation board features the am186es, high-per- formance, 80c186-compatible, 16-bit embedded con- troller, and the pcnet-isa ii high performance, 16-bit, single-chip ethernet controller for isa. the microcontroller section consists of the am186es, 512 kbytes flash and 512 kbytes sram. the ether- net section consists of a pal for glue logic and the am79c961a pcnet-isa ii. the design takes advan- tages of the bus mastering capability of the pcnet-isa ii to achieve high performance and low system cost, while reducing the amount of software overhead on the microcontroller. communication with the net186 can be accomplished through either one of the two rs-232 serial ports or through the high speed 10 mbps ethernet 10base-t port. am186es microcontroller the am186es microcontroller and its companion am188es microcontroller integrate the functions of the cpu, non-multiplexed address bus, three timers, a watchdog timer, chip selects, interrupt controller, two dma controllers, psram controller, asynchronous serial ports, programmable bus sizing, and program- mable i/o (pio) pins on one chip. compared to the 80c186/188 microcontrollers, the am186es and the am188es microcontrollers can reduce the size, power consumption, and cost of embedded systems, while in- creasing reliability, functionality, and performance. the am186es and am188es microcontrollers are part of the amd e86 family embedded microcontrollers and
2 am186 es preliminary microprocessors based on the x86 architecture . the e86 f amily includes the 80c186, 80c188, 80l186, 80l188, am186em, am188em, am186eml v , and am188eml v microcontrollers , as w ell as the am386 sx, am386 dx, and am486 de microprocessors . pcnet-isa ii ethernet contr oller the am79c961a pcnet-isa ii ether net controller , a sin- gle-chip ether net controller , is a highly integ r ated b us- master ing ether net controller with a b uilt in isa b us and phy la y er (manchester encoder/decoder and 10base- t tr ansceiv er). the 16-bit isa interf ace mak es an ideal str aightf orw ard connection to an x186 style local b us . the pcnet-isa ii has tw o f eatures which, while not im- plemented in the net186, w ould be v er y useful f or cer- tain embedded netw or king control applications: full duple x oper ation (making it possib le to tr ansmit and re- ceiv e pac k ets at the same time , f or a combined bidirec- tional data tr ansf er r ate of up to 20 mbps) and magic p ac k et t echnology (making it possib le to remotely w ak e up a sleeping system on an ether net node). the pcnet-isa ii is a v ailab le in either 132-pin pqfp (plastic quad at pac kage) or 144-pin tqfp (thin quad at pac kage). the net186 is a v ailab le in the 144-pin tqfp , speci cally designed to reduce par t count and cost, and to address applications where higher system throughput is desired. the pcnet-isa ii ether net controller is par t of the amd pcnet f amily of single-chip ether net controllers based on the or iginal lance/clance architecture . other members include the am79c965 pcnet-32 (f or vl or other gener al 32-bit b us en vironments) and the am79c970a pcnet-pci ii (f or pci b us en viron- ments). lik e the pcnet-isa ii, the pcnet-32 and the pcnet-pci ii are 10 mbps ether net controllers . the last member of the pcnet f amily is the am79c971 pcnet- f ast , a 10/100 mbps ether net controller . b loc k dia gram ucs 186es int0 hold hlda ardy lcs mcs0 22v10 eeprom we oe 29f400 (512kb) byte ce we oe 256x16 sram (512kb) ce ior iow memr memw irq drq dack iochrdy aen ref iocs16 smemr reset 79c961a tl7705a reset res wr rd whb wlb rd whb wlb memwr memrd 10base-t n/c +5 v 20 mhz 4 20, 25 33, 40 mhz 2 each rs-232 hlda clka lcs adx0 whb wlb rd +5 v ucs adx data irq hold iochrdy aen rcs sbhe hlda master memwr rcs memrd
trademarks copyright ? 1998 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. am186, am386, am486, am29000, b imr, eimr, eimr+, gigaphy, himib, ilacc, imr, imr+, imr2, isa-hub, mace, magic packet, pcnet, pcnet- fast , pcnet- fast +, pcnet-mobile, qfex, qfexr, quasi , quest, quiet, taxichip, tpex, and tpex plus are trademarks of advanced micro devices, inc. microsoft is a registered trademark of microsoft corporation. product names used in this publication are for identitcation purposes only and may be trademarks of their respective companies.
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